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40 hours - imec the Netherlands

Student Project: Neuromorphic Event-based Restricted Boltzmann Machines in FPGA

Job details

Traineeship

Restricted Boltzmann Machines (RBMs) represent fundamental elements in Deep Belief Networks (DBNs).

What you will do

Restricted Boltzmann Machines (RBMs) represent fundamental elements in Deep Belief Networks (DBNs). These types of architectures set the current state-of-the-art performance in a variety of task including speech analysis, image classification and motor control. The implementations of RBMs and DBNs in neuromorphic hardware can result beneficial for a variety of reasons which include:

  1. Concurrency in processing - memory and computation are co-localized.
  2. Event-based processing - only process information when needed.
  3. Low power consumption.
  4. Low-latency.
  5. Compatibility with embedded systems.

The focus of this project is the synthesis of Spiking Restricted Boltzmann Machines (SRBM) in FPGA fabric. During the project we will explore bio-inspired learning algorithms as Spike Timing Dependent Plasticity (STDP) and event-driven Contrastive Divergence (eCD) in both supervised and unsupervised learning scenarios. The project main goal is to develop a digital implementation in FPGA of a Spiking Restricted Boltzmann Machine (SRBM) and apply this architecture in real-life inference and classification tasks using imec-nl state-of-the-art sensors.

Main tasks:

  • (M1) Run, understand the already available simulations and literature. The student should be able to modify the SRBM architecture and its leaning algorithm.  Understand supervised and unsupervised training for the SRBM.
  • (M2, M3) The second task is to determine tradeoffs of layers /parameters / bit-precision of the SRBM that can be tuned while maintaining classification accuracy.
  • (M4-M7) Set up an event-based VHDL architecture for the SRBM, this architecture will include the following macro-blocks.
  1. Address Event Representation block. This block will take care of communication of input and output spikes.
  2. Neurons Core Layer, which will include neurons current state and neuron state update logic.
  3. Synaptic weight memory block.
  4. STDP/eCD Learning block (optional).
  • (M8-M9) The final task is to determine the computational cost of the SRBM in bio-signal classification tasks. The architecture will be characterized in terms of latency and power per synaptic events. Explore the latency vs accuracy trade-off. Compare the results with state-of-the-art systems (GPU/CPU based). 

What we do for you

As a student in the Neuromorphic team you get the chance to contribute in several challenges to the design of efficient brain-like chips: scalable, energy-efficient, highly flexible network architectures that can learn with incredible efficiency. The student will benefit by closely interacting with research scientists and engineers at imec-nl. 

Who you are

  • Motivated MSc student in Computer Science and Electrical Engineering.
  • Available for 9-12 months. Task duration is noted monthly for each task. (es. M3 stands for 3rd month from the start of the project).
  • Programming skills: Strong in VHDL and one of C++, Python, Matlab.
  • Proven knowledge of VHDL and FPGA, ability to work independently with digital logic design and expand knowledge in the field.
  • Basic knowledge of neural networks, machine learning.
  • Good written and verbal English skills.

Interested

Click on ‘apply’ to submit your application. You will then be redirected to e-recruiting.

Please be advised that non-EU/EEA country students that are studying outside of the Netherlands, need to have a work-permit to be able to do an internship at imec the Netherlands.

Please note that to be considered for an internship you need to be registered as a student during the entire internship period. Formal documentation of which may be requested at any time.

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