To scale up the work done by previous students, we want to work toward tiling the processing cores. NoC is a solution to build high-performance scalable GALS architectures, optimized for brain-inspired computing. We would like to design a NoC to tile our neuromorphic processing cores.
Connectivity is one of the main challenges in neural network deployment in electronic circuits. In a practical neural network, a neuron may connect to thousands of neurons to build a neural network. In the Neuromorphic group of imec, we are interested to build advanced neuromorphic processing technologies for Spiking Neural Networks (SNN). In an SNN, the neurons talk with each other using spikes. Spikes can be encoded in a small packet of data known as Address Event Representation (AER) . In this case, a packet-switched Network on Chip (NoC) is a particularly interesting solution as a scalable technology for communicating the small packet of data   . Throughput, latency, energy consumption and scalability are the main features to be optimized for this NoC. On the other hand, features like reliability can be compromised as much as it does not disturb the proper functionality of SNN.
As the number of neurons in a chip increases, the main performance bottleneck is due to communication overhead. This requires high throughput NoC optimized for small packets of AER data. Multi-casting techniques can increase throughput and reduce power consumption in SNN applications  and should be studied during this project.
Additionally, in many SNNs, information is mostly encoded in the time of the spikes. This requirement enforces a tight restriction on communication latency. Sometimes a delayed packet should be dropped because it carries wrong information. The design of an efficient packet-dropping mechanism may be part of this project. Additionally, we may look at the mechanism to compress packets that goes to the same destination (making a mini frame) .
A fully synchronous chip is not scalable and not optimized for sparse event-driven applications. Therefore, it is desired to designed asynchronous communication. The processing tiles connected to each router can be asynchronous  or locally synchronous which results in a GALS architecture . The asynchronous design normally reduces the throughput which is a challenge that needs to be addressed in this project using the state-of-the-art techniques. This project involved a pre-study of the available approaches, propose a new optimized NoC for the mentioned requirements, simulation and implementation in hardware and an FPGA demonstration by integrating the NoC with the available neuromorphic processing cores. Optionally, it is desired to extend the design with a chip to chip connectivity scheme to scale up the system using a multi-FPGA demonstration. This project is aligned with the European TEMPO project  and the results will be used in the target hardware.
The project duration is of 9 months. This project results in a neuromorphic FPGA demonstrator system with possible usage in future neuromorphic SoC of imec. The outcome of the project may be published in high impact journals and might as well be patented.
We seek very motivated candidates with an electrical engineering background, with strong knowledge of the digital design workflow in FPGA and familiarity with NoC algorithms and design. Knowledge of digital asynchronous design in FPGA and Spiking Neural Networks is a plus.
References:  https://isn.ucsd.edu/courses/7...  M. Davies et al., "Loihi: A Neuromorphic Manycore Processor with On-Chip Learning," in IEEE Micro, vol. 38, no. 1, pp. 82-99, January/February 2018.  F. Akopyan et al., "TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 10, pp. 1537-1557, Oct. 2015.  L. A. Plana, et al., "An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator," Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), Newcastle upon Tyne, 2008, pp. 215-216.  B. Son et al., "4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation," ISSCC, 2017  https://cordis.europa.eu/project/id/.
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