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40 hours - Graimatterlabs

Student Project: Asynchronous Network on Chip

Job details


Design and implementation of a high performance asynchronous Network on Chip to be used in a GALS (globally Asynchronous Locally Synchronous) neuromorphic processor

GRAI MATTER LABS  is a neuromorphic company dedicated to delivering low power processors for bio-inspired signal processing on the edge. The architecture is based on 2D array of basic computing units (neurons). These computing units are connected together using conventional communication architecture (synchronous network on-chip). As number of processing cores in the chip increases, main performance bottlenecks are due communication overhead.

In biology, communication between different cores are arranged in hierarchical, asynchronous manner. There is denser local-connectivity in time-aligned manner, while global connectivity is asynchronous.

Based on the above, the proposed research focusses on applying GALS approach to study and build a communication infrastructure for the computing fabric. The study involves benchmarking the current approach against the new proposal. Consequently, a simulation model and scalable hardware implementation framework is desired outcome.

This project is aimed to design an asynchronous Network of GrAI-One cores on a chips which satisfy the latency/bandwidth requirement for the target applications.


  • A. G. Andreou et al., "Real-time sensory information processing using the TrueNorth Neurosynaptic System," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 2911-2911.
  • L. A. Plana, J. Bainbridge, S. Furber, S. Salisbury, Y. Shi and J. Wu, "An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator," Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), Newcastle upon Tyne, 2008, pp. 215-216.
  • M. Davies et al., "Loihi: A Neuromorphic Manycore Processor with On-Chip Learning," in IEEE Micro, vol. 38, no. 1, pp. 82-99, January/February 2018.


The master thesis would consist of the following activities:

  • Became familiar with GrAI-One neuromorphic processors.
  • Design space Exploration for asynchronous NoCs
  • Design and simulate an asychronous NoC and measure performance indexes Implementation of the NoC in HDL and the corresponding testbenches
Required Skills 
Must have:
Master student with electrical/computer engineering background
Available for a period of 9-12 months
Strong in digital design and RTL development (Verilog or VHDL)
Strong in one of SystemC, C++, Python, MATLAB or OCaml.  
Good to have:
Basic knowledge in asynchronous design and Network on Chip
Basic knowledge of bio-inspired event-driven processing

Please be advised that non-EU/EEA country students that are studying outside of the Netherlands, need to have a work-permit to be able to do an internship in the Netherlands.

To Apply Please send your CV (including contact detail) and other supporting documents to 
Ajay Kapoor ( 

Job details
  • Asynchronous
  • Network On Chip
  • Neuromorphic
  • Digital Hardware Design

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