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40 hours - imec the Netherlands

Neuromorphic Event-based Restricted Boltzmann Machines in FPGA

Job details


The project main goal is to develop a digital implementation in FPGA of a Spiking Restricted Boltzmann Machine (SRBM) and apply this architecture in real-life inference and classification tasks using imec-nl state-of-the-art bio-sensors.

What you will do

In this project you will focus on the synthesis of spiking Restricted Boltzmann Machines (SRBM) which will be analyzed as Synaptic Sampling Machines and Generative Models [1]. Inference and learning in RBMs and DBNs is achieved via Markov Chain Monte Carlo procedure called Gibbs sampling. It has already been shown that this procedure can be implemented using spiking neurons under certain circumstances [2].

This project will explore relations among neuromorphic Restricted Boltzmann Machines and current state-of-the-art deep learning mechanisms as DropConnect and Dropouts. During the course of the project, we will explore bio realistic learning rules as Spike Timing Dependent Plasticity (STDP) and event-driven Contrastive Divergence (eCD) as the main mechanism for weight update. 

  • Run, understand the already available simulation. The student should be able to modify the SRBM architecture and its leaning algorithm.
  • The second task is to determine tradeoffs of layers / parameters / bit-precision of the SRBM that can be tuned while maintaining classification accuracy. Explore online learning rules as STDP and eCD [3,4,5]. 
  • Set up an event-based VHDL architecture for the SRBM, this architecture will include the following macro-blocks.
  1. Address Event Representation block. This block will take care of communication of input and output spikes.
  2. Neurons Core Layer, which will include neurons current state and neuron state update logic.
  3. Synaptic weight memory block.
  4. STDP/eCD Learning block (optional).
  • The final task is to determine the computational cost of the SRBM in bio-signal classification tasks to conclude whether the event-based processing pays off. The architecture will be characterized in terms of latency and power per synaptic events. Explore the latency vs accuracy trade-off. Compare the results with state-of-the-art systems  (GPU/CPU based).

What we do for you

In collaboration with your colleagues, you will work on a number of challenges to the design of efficient brain-like chips: scalable, energy-efficient, highly flexible network architectures that can learn with incredible efficiency.

Who you are

  • Bachelor’s/Master’s student in Electrical/Computer Science.
  • Available for a period of 9 months.
  • Programming skills: one of Matlab/Python/C++/VHDL.
  • Proven knowledge of VHDL and FPGA, ability to work independently with digital logic design.
  • Basic understanding of neural networks, machine learning.
  • Good mathematical skills.


Click on ‘apply’ to submit your application. You will then be redirected to e-recruiting. If you know someone who could be the right fit for the job click on ’refer’.

Please be advised that non-EU/EEA country students that are studying outside of the Netherlands, need to have a work-permit to be able to do an internship in the Netherlands.

Job details
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